Nice detailed comment! It's also interesting how Cerebras WSE deals with defects because it's unavoidable. Cerebras actually routes around the failing GPU cells and reconfigures it. Elegant way to deal with it.
Test and binning is interesting. When dealing with chiplets, people usually think it's obvious that going smaller to chiplets is …
Nice detailed comment! It's also interesting how Cerebras WSE deals with defects because it's unavoidable. Cerebras actually routes around the failing GPU cells and reconfigures it. Elegant way to deal with it.
Test and binning is interesting. When dealing with chiplets, people usually think it's obvious that going smaller to chiplets is always better for the system because of better yield. Reality is quite a bit more complex. I've been thinking about this.
The cool part is that Cerebras's WSE is the only commercial implementation of the idea that works given the many intervening decades between now and the original conception. Built-in redundancy and routing around the defective cell is an absolute engineering marvel. For certain use cases, e.g., LLMs, the WSE is a compelling value prop.
Yes, if you have ever built a gaming PC, you might have purchased a slightly less performant CPU that came about as a result of binning. Moreover, nowadays, it is not enough to make the chip with minimal attention to packaging - you also have to package it precisely and scalably with more advanced techniques. I will be careful with using terms such as 'chipsets' since they can mean different things to different people. But if you are interested in this space, you should be on the lookout for people build out their advanced packaging capacity...
I just attended a whole day on die to die interconnect and chiplets were being referred to any smaller piece of what would have been an SoC, serving a particular function like logic, io, power etc.
Nice detailed comment! It's also interesting how Cerebras WSE deals with defects because it's unavoidable. Cerebras actually routes around the failing GPU cells and reconfigures it. Elegant way to deal with it.
Test and binning is interesting. When dealing with chiplets, people usually think it's obvious that going smaller to chiplets is always better for the system because of better yield. Reality is quite a bit more complex. I've been thinking about this.
The cool part is that Cerebras's WSE is the only commercial implementation of the idea that works given the many intervening decades between now and the original conception. Built-in redundancy and routing around the defective cell is an absolute engineering marvel. For certain use cases, e.g., LLMs, the WSE is a compelling value prop.
Yes, if you have ever built a gaming PC, you might have purchased a slightly less performant CPU that came about as a result of binning. Moreover, nowadays, it is not enough to make the chip with minimal attention to packaging - you also have to package it precisely and scalably with more advanced techniques. I will be careful with using terms such as 'chipsets' since they can mean different things to different people. But if you are interested in this space, you should be on the lookout for people build out their advanced packaging capacity...
I just attended a whole day on die to die interconnect and chiplets were being referred to any smaller piece of what would have been an SoC, serving a particular function like logic, io, power etc.
Yeah, but it is very unclear what the value proposition is unless you are talking about a specific configuration.