9 Comments

Given that Intel's chip is bigger in die size, should not the actual yield rate be lower for the same defect density?

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Absolutely right. I assumed a 10mm X 10mm chip. Filling in the right die size in my linked spreadsheet should find the correct yields.

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Very helpful. And timely given the announcement from Intel. Now to go back and re-read that… 🙏

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Great! My intention was to help decode the news a bit more from a technical point of view.

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Something that came to mind while reading: I remember looking into the "bathtub curve" when researching the topic of predictive analytics for large capital machinery.

Essentially what is being described during the burn-in period (going from D0 > 0.40 to <0.40 to <0.10) is that first edge of the bathtub before you get to the flat bottom. But, with age, wear etc, presumably the reverse happens? Meaning, defect rates start to grow again as equipment reaches the end of its expected life? TSMC, for example, opens a new fab for each node, but runs existing fabs for prior nodes...as long as possible if there is demand for that node, I would imagine, but I would imagine at some point equipment needs to be upgraded etc as failure rates cross some threshold.

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The early end of the bathtub curve is what most people care about in semi. I have not heard of anyone talk about the failures close to end of life. This is probably because by the time that happens, the node itself has reached obsolescence in terms of its usability, and foundries discontinue production. This usually never makes major news.

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Thanks Vikram , great info

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Thanks!

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So you’re telling me that the chip in my kid’s annoying toy requires a facility as clean as an operating room?!

I’m sure there’s some insane engineering going into the machines and tools required to fabricate these dies. Topic for another article perhaps!

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