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2dEdited

Lucid! I had not previously noticed the problem of decreasing gate voltage colliding with immovable sub threshold slope as one of the reasons scaling ended. Interesting that several limits all coincided about the same scale.

Carver Mead in the mid-1960s presented a comprehensive description of scaling of semiconductor devices, and published a prediction for sub-micron devices (expected as the limit to lithography), Dennard reduced that general case to a concise set of rules just for CMOS which provided a road ahead with constant power per area that everyone could drive. Sometimes less is Moore.

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Thanks! Any idea what that Mead paper is called? If there is a limit to lithography that someone as influential as Mead has written about, then I ought to read it.

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Interesting, I could not find it. I was relying on Carver's in-person statement about having given the lecture in mid-1960s and predicted device limits in a paper, but it looks like the paper was submitted for publication in 1971. If there was an earlier one it is curious there are no citations to it from this one: https://hasler.ece.gatech.edu/Published_papers/Technology_overview/Hoeneisen_Mead_1972a.pdf

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Thanks! I'll check this one out.

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