A detailed explanation of Robert Dennard's exact rules to scale a MOS-transistor's dimensions that resulted in more transistors on a single chip without any thermal penalty.
Lucid! I had not previously noticed the problem of decreasing gate voltage colliding with immovable sub threshold slope as one of the reasons scaling ended. Interesting that several limits all coincided about the same scale.
Carver Mead in the mid-1960s presented a comprehensive description of scaling of semiconductor devices, and published a prediction for sub-micron devices (expected as the limit to lithography), Dennard reduced that general case to a concise set of rules just for CMOS which provided a road ahead with constant power per area that everyone could drive. Sometimes less is Moore.
Thanks! Any idea what that Mead paper is called? If there is a limit to lithography that someone as influential as Mead has written about, then I ought to read it.
Interesting, I could not find it. I was relying on Carver's in-person statement about having given the lecture in mid-1960s and predicted device limits in a paper, but it looks like the paper was submitted for publication in 1971. If there was an earlier one it is curious there are no citations to it from this one: https://hasler.ece.gatech.edu/Published_papers/Technology_overview/Hoeneisen_Mead_1972a.pdf
Thanks Vikram! In addition to the points you covered here so nicely, another factor that prevents true Dennard scaling are the quantum mechanical phenomena, especially tunneling, that become more and more important (likely) as the distances gating current flows decrease. Once we approached a gate thickness measured in nanometers, leak currents become significant. All this is in addition to the difficulty providing power through more and ever-smaller vias and the other factors you already described. All these factors contribute to more heat, something semiconductors especially at nanometer scale really don't like.
To go back to concrete examples: Intel's Pentium IV marked, IMHO, a true "hard stop" in their quest to keep increasing frequencies. The idea of having the CPU performing more and more tasks by few ( first one, later two) cores by running a core really, really fast hit a wall. With the Pentium IV, that wasn't helped by a design with a very long pipeline that caused trouble when it stalled. Which happened often enough. The entire industry then turned to multiple core designs and increasing speed and efficiency by including specialized circuitry (SIMDs) in the cores.
Thanks for the detailed reply! Yeah sub threshold slope won’t scale due to quantum mechanical gate tunneling and resulting leakage… I didn’t get too deep into it. Thanks for adding to the info!
Lucid! I had not previously noticed the problem of decreasing gate voltage colliding with immovable sub threshold slope as one of the reasons scaling ended. Interesting that several limits all coincided about the same scale.
Carver Mead in the mid-1960s presented a comprehensive description of scaling of semiconductor devices, and published a prediction for sub-micron devices (expected as the limit to lithography), Dennard reduced that general case to a concise set of rules just for CMOS which provided a road ahead with constant power per area that everyone could drive. Sometimes less is Moore.
Thanks! Any idea what that Mead paper is called? If there is a limit to lithography that someone as influential as Mead has written about, then I ought to read it.
Interesting, I could not find it. I was relying on Carver's in-person statement about having given the lecture in mid-1960s and predicted device limits in a paper, but it looks like the paper was submitted for publication in 1971. If there was an earlier one it is curious there are no citations to it from this one: https://hasler.ece.gatech.edu/Published_papers/Technology_overview/Hoeneisen_Mead_1972a.pdf
Thanks! I'll check this one out.
Thanks Vikram! In addition to the points you covered here so nicely, another factor that prevents true Dennard scaling are the quantum mechanical phenomena, especially tunneling, that become more and more important (likely) as the distances gating current flows decrease. Once we approached a gate thickness measured in nanometers, leak currents become significant. All this is in addition to the difficulty providing power through more and ever-smaller vias and the other factors you already described. All these factors contribute to more heat, something semiconductors especially at nanometer scale really don't like.
To go back to concrete examples: Intel's Pentium IV marked, IMHO, a true "hard stop" in their quest to keep increasing frequencies. The idea of having the CPU performing more and more tasks by few ( first one, later two) cores by running a core really, really fast hit a wall. With the Pentium IV, that wasn't helped by a design with a very long pipeline that caused trouble when it stalled. Which happened often enough. The entire industry then turned to multiple core designs and increasing speed and efficiency by including specialized circuitry (SIMDs) in the cores.
Thanks for the detailed reply! Yeah sub threshold slope won’t scale due to quantum mechanical gate tunneling and resulting leakage… I didn’t get too deep into it. Thanks for adding to the info!
Thank you so much!